Tutoriais SBMicro
Tutorial I – MOSFET Series Resistance in the Nanoscale Era: From Planar CMOS to FinFETs and GAA Devices
Adelmo Ortiz-Conde
Simón Bolívar University, Caracas, Venezuela
Abstract:
The classical planar MOSFETs were replaced with 3D FinFETs in 2012, and with gate-all-around (GAA) Nanosheet FETs in 2025. The GAA nanosheet FETs used in the industry are composed of nanosheets stacked vertically, with the current flowing horizontally. In research labs, new vertical transport GAA VT-FETs are being developed; these are composed of nanosheets stacked horizontally, with the current flowing vertically. The performance of advanced MOSFETs is strongly limited by the presence of parasitic series resistances. The asymmetry between drain and source resistance is crucial for the particular case of Vertical Transport Field Effect Transistors. This presentation reviews and scrutinizes the extraction methods currently used to determine the values of parasitic series resistances from the measured drain current.
Short-bio:
Adelmo Ortiz-Conde received the professional Electronics Engineer degree from Universidad Simón Bolívar (USB), Caracas, Venezuela, in 1979 and the M.E. and Ph.D. from the University of Florida, Gainesville, in 1982 and 1985, respectively. From 1979 to 1980, he served as an instructor in the Electronics Department at USB. In 1985, he joined the technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high voltage integrated circuits. In 1987, he returned to the Electronics Department at USB where he was promoted to Full Professor in 1995. He was on sabbatical leave at University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998. He also was on sabbatical leave at “Centro de Investigaciones y Estudios Avanzados” (CINVESTAV) National Polytechnic Institute (IPN), Mexico City, Mexico, from October 2000 to February 2001. He has coauthored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (2012 Springer reprint of the original 1st ed. 1998, http://dx.doi.org/10.1007/978-1-4615-5415-8 ), over 200 international technical journal and conference articles (including 22 invited review articles). His present research interests include the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is an EDS Distinguished Lecturer and the Vice-Chair of IEEE’s CAS/ED Venezuelan Chapter. He was editor of IEEE Electron Device Letters in the area of Silicon Devices and Technology from 2009 to 2018. He was the Region 9 Editor of IEEE EDS Newsletter from 2000 to 2005. He is a Member of the Editorial Advisory Board of various technical journals: Microelectronics and Reliability, “Universidad Ciencia y Tecnología” and “Revista Ingeniería UC”. He regularly serves as reviewer of several international journals and conferences. He was one of the founders of the first IEEE International Caracas Conference on Devices, Circuits, and Systems (ICCDCS) in 1995. In order to make it more international, this conference changed its name to “International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS)” in its sixth edition in 2006. Since 2019, this conference has been sponsored by the IEEE Electron Devices Society (EDS) under the name of “IEEE Latin America Electron Devices Conference (LAEDC)”.
Tutorial II – SiC Fabrication in a Silicon Fab
Victor Veliadis
Executive Director and CTO of PowerAmerica and NC State professor
Abstract:
SiC chips are displacing their incumbent silicon counterparts in several high-volume power applications. As SiC market share continues to grow, the industry is lifting remaining barriers to mass commercialization including the higher-than-silicon chip cost that increases disproportionately with area, defects that limit chip yield and area, reliability and ruggedness concerns, and the need for a trained workforce to skillfully insert SiC devices into power electronics circuits. With respect to fabrication, the SiC industry is successfully leveraging the fully depreciated legacy silicon fab infrastructure, and is making the relatively small financial investments that allow mature silicon fabs to process SiC. Consequently, SiC chip fabrication alongside silicon has emerged as a cost-effective model that exploits silicon manufacturing economies of scale. In this presentation, key aspects of SiC fabrication technology will be summarized with an emphasis on non-silicon-compatible processes streamlined for mass SiC manufacturing. The latter include dry etching, substrate thinning, heated implantation and high temperature annealing, CTE-matched metallization, ohmic contact formation, improved gate oxide interface quality, transparent wafer handling, as well as edge termination techniques that maximize blocking voltage. Furthermore, advantages and challenges of trench vs. planar MOSFETs will be briefly discussed.
Short-bio:
Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a Manufacturing USA Institute accelerating SiC and GaN power semiconductor chip and electronics commercialization. At PowerAmerica, he has managed over $150 million across 200+ projects advancing manufacturing and workforce development, and is currently managing a $64M DOE renewal. Prior to joining Power America in 2016, Dr. Veliadis spent 21 years post-Ph.D. in the semiconductor industry, where his work included design, fabrication, and testing of SiC devices, GaN devices for radar systems, and financial and operations management of a commercial semiconductor fab. He is an NC State professor, an IEEE and NAI Fellow, and holds 27 U.S. patents, 173 publications, 13 book chapters, and one co-edited book. He has delivered over 250 keynotes and invited presentations.
Tutorial III – ISFET – The MOSFET as a sensor
José Alexandre Diniz
Full Professor, FEEC/Unicamp
Abstract:
ISFET (Ion Sensitive Field Effect Transistor) The big difference between an ISFET (Ion Sensitive Field Effect Transistor) and a conventional MOSFET (Metal Oxide Semiconductor FET) is the absence of the upper electrode on the gate oxide of the device. In the case of an ISFET, the gate reference electrode with the solution (of chemical or biological materials), which is in contact with the gate oxide (dielectric), works as the upper electrode, inducing the channel in the semiconductor and enabling the conduction of electric current between source and drain terminals. On these two terminals, there are polymer layers that serve as a barrier against chemical or biological solutions. Therefore, the choice of the gate oxide is of great importance, since it must present chemical stability when in contact with the solution that will be measured. The solution pH is the primary parameter measured. The gate dielectric chosen for application as a pH sensor must perform measurements in acidic and basic media and form hydroxyl and hydrogen bonds. This ability is associated with highly electronegative atoms, such as fluorine, oxygen, and nitrogen. Furthermore, ISFETs can detect water contamination metals, DNA, RNA, enzymatic, antigen-antibody, and cell-related targets. Thus, thin films of SiNx, TiOx, TaOx, AlOx, and AlN were chosen as gate dielectrics because they are compatible with chemical or biological substances. Various results from the literature will be presented in this invited talk. Also, it will be shown that ISFET devices are essential sensors for future instrumentation, as they enable the detection of various chemical and biological species, using different materials as gate dielectrics, electrodes, and conduction channels.
Short-bio:
José Alexandre Diniz holds a degree in Physics, a master’ s degree, and a doctorate in Electrical Engineering from the State University of Campinas (Unicamp), obtained in 1988, 1992, and 1996, respectively. He completed his postdoctoral studies from 1996 to 1998 in the Department of Semiconductors, Instruments, and Photonics (DSIF) of the Faculty of Electrical and Computer Engineering (FEEC) at Unicamp, supported by a FAPESP scholarship. In January 1998, he undertook a visiting researcher internship at the University of Florida in Gainesville, FL, USA. He was a PQ researcher at Unicamp Center for Semiconductor Components and Nanotechnologies (CCSNano) from 1999 to 2002. Since 2002, he has been a professor at FEEC/Unicamp in the area of electronics, serving as an associate professor from July 2007 to April 2017 and currently as a full professor. His research continues at CCSNano, where he served as Associate Director from 2005 to 2010 and as Director from 2010 to 2016. He was Vice President of the Brazilian Microelectronics Society (SBMicro) from 2016 to 2020. He was the director of FEEC/Unicamp from May 2019 to April 2023. He has published over 210 articles in indexed journals and international conferences. He has supervised 20 doctoral and 21 master’s students. Prof. Diniz is a CNPq Research Productivity Fellow – Level 1C. He has experience in Microelectronics, with an emphasis on Micro and Nano fabrication based on MOS, MEMS, HBT, and graphene technologies. Due to his contributions in the field, he received the 2022 Father Landell de Moura Award, promoted by the Brazilian Society of Microelectronics (SBMicro), and the 2024 Zeferino Vaz Award for academic recognition, promoted by Unicamp.
Tutorial IV – Charge Trapping in Semiconductor Devices: From Device Level Modeling
to Circuit Analysis
Gilson I. Wirth
Electrical Engineering Dep., UFRGS –
Federal Univ. of Rio Grande do Sul, Brazil
Abstract:
Charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is a major source of noise in modern MOS devices. It also causes Bias Temperature Instability (BTI). A comprehensive physics-based modeling and simulation approach for BTI, RTN and low-frequency noise is reviewed, discussed and summarized. It allows for the derivation of analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI (aging) using a single modeling framework, where model parameters are the same in frequency and time domain. Noise and BTI levels can vary by several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. To ensure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability in noise and BTI.
Time domain analysis is relevant for the analysis of digital and mixed-signal circuits. In digital circuits, the RTN chronological statistics, especially trap occupancy switching, have direct impacts on circuit performance and reliability, as degradations like jitter of signals happen when a trap switches state. The area scaling of RTN induced jitter (phase noise) and its variability is detailed and discussed, aiming to support circuit designers in transistor sizing towards a more reliable design. The applicability of the model here presented to the evaluation of logic gates and circuits is also discussed.
Short biography:
Gilson Wirth is currently a full professor at the Electrical Eng. Dep. at Univ. Federal do Rio Grande do Sul – UFRGS, Porto Alegre, Brazil. He received the B.S.E.E and M.Sc. degrees from UFRGS – Univ. Federal do Rio Grande do Sul, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund (TU Dortmund), Dortmund, Germany. His research work focuses on modeling and electrical simulation of charge trapping in the context of Bias Temperature Instability (BTI), Low-Frequency Noise (1/f and RTN) and Hot Carrier Degradation (HCD). He has also worked on ionizing radiation effects (TID and SET/SEU) on semiconductor devices. He is currently a Distinguished Lecturer of the IEEE Electron Devices Society. He also was a Distinguished Lecturer of the IEEE Circuits and Systems Society (term 2010-2011). A list of publications may be found e.g. at
https://www.scopus.com/authid/detail.uri?authorId=8700162500
Tutoriais SBCCI
Tutorial I – Evolutionary Optimization Techniques for Robust Analog Circuit Design
Prof. Fabián Olivera
Federal University of Rio de Janeiro (UFRJ), Brazil
Abstract:
Manufacturing process variations are critical in analog circuit design, often leading to significant performance degradation. In modern technologies, optimization becomes increasingly challenging due to the complexity and nonlinearity of the analog design space. In this tutorial, evolutionary algorithm-based techniques are presented to address these challenges. By incorporating statistical analysis and robustness metrics into the evolutionary loop, these methods enable the automatic synthesis and optimization of analog circuits with enhanced tolerance to variability. We will illustrate their application to analog building blocks such as voltage references, static random access memories (SRAMs), charge pumps, among others. Practical implementation aspects and integration with traditional simulators will also be discussed, highlighting how evolutionary techniques can improve design efficiency and circuit reliability in advanced technologies.
Short-bio:
Fabián is an electronic engineer, graduated from the Universidad de la República (Udelar) in Montevideo, Uruguay. He received his M.Sc. (2013) and Ph.D. (2017) degrees in Science from the Federal University of Rio de Janeiro (UFRJ), Brazil. Since 2025, he has been a professor in the Electrical Engineering Program (PEE) at COPPE/UFRJ, where he currently serves as Academic Coordinator. Fabián holds a CNPq Research Productivity Fellowship (Level C) and a Young Scientist of our State (JCNE) fellowship from FAPERJ. Fabián is a Senior Member of the Institute of Electrical and Electronics Engineers (IEEE) and served as Chair of the IEEE Circuits and Systems Society (CASS) Rio de Janeiro Chapter from 2022 to 2026. He is also a member of the Brazilian Society of Microelectronics (SBMicro), currently serving as board member for the 2024-2027 term. He has been actively involved in the organization of national and international events. He served as program chair of the IBERCHIP Workshop in 2023 and 2024, held in Ecuador and Uruguay, respectively. He also coordinated the tutorial sessions at SBCCI Chip in Rio 2023 in Brazil and was the general chair of the IEEE CASS Latin American Symposium on Circuits and Systems (LASCAS) 2025, held in Bento Gonçalves, Brazil. His research trajectory, which began in 2009, is focused on microelectronics, specializing in the design of analog and mixed-mode integrated circuits, with an emphasis on ultra-low-power applications. He also has experience in the development of computer-aided design tools for the design and optimization of analog circuits.
Tutorial II – Artificial Intelligence: Why EE students should learn it (internally)
Prof. Volnei A. Pedroni
Federal Technological University of Paraná (UTFPR), Brazil and Caltech, USA
Abstract:
Artificial Intelligence (AI) has become a major source of novel, sophisticated solutions for complex engineering problems, from object detection to autonomous vehicles, smart manufacturing to cancer diagnosis, speech detection to text translation, and much more. And that includes also the microelectronics field, with AI already present in a number of tasks, e.g., layout optimization, fabrication processes control, and defect detection. Discussing the (proper) adoption of AI to the EE curriculum seems then highly recommended. The core purpose of this presentation is to highlight how much AI has to do with EE and how much our students would stand to loose in case proper AI training is not offered to them. To be effective, the presentation will take into consideration that participants not familiar with AI construction might be present, so a detailed review of AI fundamentals will be included. The presentation will be divided into four parts, being one dedicated to the review, another to Machine Learning, and the other two to Deep Learning (Discriminative and Generative). Time permitting, a case study will be also included. The topics will be accompanied by historic facts, inventors affiliations, major achievements, etc. At the end, a brief listing of the AI teaching situation in the EE Dept. of several top universities will be presented.
Short bio:
Volnei A. Pedroni received the BSc degree in Electrical Engineering from the Federal University of Rio Grande do Sul (UFRGS, 1975), and both the MSc (1990) and PhD (1995) degrees in Electrical Engineering from the California Institute of Technology (Caltech), USA. His area of expertise is Microelectronics/Chip Design, having the development of dedicated neural network chips (for AI) been at the core of his PhD work. He was the founder of LME (2010), the microelectronics lab of UTFPR, which allowed UTFPR to be one of the first institutions in Brazil to provide chip fabrication (via MOSIS) to regular undergrad students. The areas of ASICs, FPGAs, and Circuit Design with VHD are of particular interest. He has a number of publications in the field, including two books by MIT Press: Circuit Design with VHDL (a bestseller, in its 3rd edition) and Finite State Machines in Hardware: Theory and Design, with VHDL and SystemVerilog. Prof. Pedroni did collaboration with Caltech (USA), University of Trento (IT), and University of Modena (IT). After retiring from UTFPR in 2017 (but continuing associated for two more years as a Volunteer Professor), he became a regular Invited Professor in the Department of Electrical Engineering of Caltech, a work that lasted until 2025. Recently, Prof. Pedroni has also acted occasionally as a tutor on “Inside AI”. The main courses taught by Prof. Pedroni are the following: At UTFPR: Semiconductor Devices, Electronic Amplifiers, Signals and Systems, Microelectronics (chip design and layout), Statistics, Digital Circuit Design with VHDL. At Caltech: Semiconductor Devices, Analog Circuit Design, Digital Circuit Design with VHDL, Advanced Digital Circuit Design with VHDL. At University of Trento and University of Modena: Digital Circuit Design with VHDL.
Tutorial III – RISC-V in Practice: From the ISA to a Silicon-Proven Core
Prof. Fernando Gehm Moraes
School of Technology, Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil
Abstract:
This tutorial outlines the progression from the RISC-V instruction set architecture (ISA) to a functional silicon implementation. It is structured in three parts. Part I presents RISC-V as an open, royalty-free, and modular ISA. It reviews the RV32I base, instruction formats, addressing modes, privilege levels (M/S/U), control and status registers, and the instruction set extension (ISE) mechanism. It also surveys the range of core implementations, from microcontroller-class designs to out-of-order high-performance computing cores, and commercial silicon and Linux-capable boards. Part II describes RS5, a parameterizable four-stage RV32I core developed at PUCRS. It provides details on the pipeline stages, interrupt and timer support, and supported extensions, including M, A, C, Zicsr, Zicond, and performance counters. It addresses hardware cryptography (AES, SHA-2/3, post-quantum ML-KEM) and vector acceleration, presenting PPA results. This part concludes with a comparison to cores such as Ibex and CV32E40P, as well as an overview of the software stack. Part III focuses on validation and physical design, including RISCOF architectural compliance, FPGA prototyping with Zephyr OS, and the ASIC design flow from RTL to GDSII. It concludes with the RS5V-SoC, fabricated in 28 nm CMOS as part of the SoC-WiMed project, and a later 65 nm tapeout incorporating the vector extension. RS5 source code and related materials are available for academic use, allowing attendees to experiment with the core and apply the concepts discussed during the tutorial.
Short bio:
Fernando Gehm Moraes is a Full Professor at the Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Brazil, and a CNPq Research Productivity Fellow (Level A). His scholarly trajectory spans four decades of contributions to VLSI design, encompassing networks-on-chip, multiprocessor systems-on-chip (MPSoCs), reconfigurable architectures, and hardware security for manycore computing platforms. He holds an Electrical Engineering degree and an M.Sc. in Computer Science from the Universidade Federal do Rio Grande do Sul (UFRGS) and completed his Ph.D. in Microelectronics at the Université Montpellier 2 (LIRMM), France, in 1994. His current research program addresses the intersection of hardware security and machine learning in manycore systems built on the open RISC-, investigating hardware Trojan detection in NoCs and RISC-V instruction-set extensions for cryptographic and neural network acceleration. Professor Moraes has authored 65 peer-reviewed journal articles, including a seminal contribution to NoCs that remains widely cited in the field. He has supervised several doctoral and master’s dissertations and continues to lead multiple externally funded research initiatives with national agencies and industry partners. He serves on the program committees of international conferences on VLSI and microelectronics design, is an associate editor for an IEEE Transactions journal, and is the Financial Director of the Brazilian Microelectronics Society (SBMicro). He is a Senior Member of IEEE.