SEMINATEC 2024 Invited Talks
1) Advanced Semiconductor Technology and Device Architectures for the Next Decade
Prof. Dr. Cor Claeys, Fellow IEEE, Fellow ECS, Distinguished Lecturer IEEE EDS, Leuven, Belgium
Semiconductor technology has known an exponential evolution in the last decades and is fully integrated in our everyday life. This necessitates implementation of novel materials, advanced design concepts and new transistor structures. Increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function, are driving microelectronic research towards 2-nm technologies. Device architectures such as FinFETs, TFETs, negative capacitance, Gate-All-Around, nanowires (NWs), nanosheets (NSs), CFET and Forksheet structures for logic and analog/RF building blocks enable System-on-Chip (SoC) applications. The strong progress achieved in silicon technology and heterogenous integration of Ge and III-V technologies on a silicon platform results in the on-chip integration of building blocks with different functionality. GaN offers unique features for RF applications used in base stations for mobile communication, complementing the performance of Si devices suffering from limited output power. A main challenge related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects. There is a commercial breakthrough of GaN devices, although dependent on the application there is a competition with SiC. Major trends in process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium” and “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. He (co)authored 16 book chapters, over 1200 conference presentations and more than 1300 technical papers. He is editor/co-editor of 70 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012- 2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. Within the Electrochemical Society, he was Chair of the Electronics & Photonics Division (2001-2003). In 2004, he received the Electronics & Photonics Division Award. In 2016 he received the Semi China Special Recognition Award for outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).
2) Recent Applications of the Lambert’s W function to device modeling
Prof. Dr. Adelmo Ortiz-Conde, Solid State Electronics Laboratory, Simón Bolívar University, Caracas, Venezuela
We present a review of recent uses of the special mathematical function known as the Lambert’s function for device modeling applications. The nowadays ubiquitous W is a multivalued special mathematical function implicitly defined as the inverse function of the linear-exponential transcendental equation , which can be solved for only when , where k represents the branch number. W was originally formulated by Leonhard Euler in 1783, and revived by Edward M. Wright in 1959 and later rescued for practical use in 1996 by Robert M. Corless and coworkers. The W function’s name “Lambert” commemorates Johann Heinrich Lambert's Transcendental Equation of 1758, and the use of the symbol “W” acknowledges the pioneering work of Wright on the subject. As far as we know, the first application of Lambert’s function to device modelling was proposed in 2000 by Banwell, specifically for the case of a diode with parasitic series resistance. Three years later in 2003, the W function was again used in electronics for the first time for MOSFET modeling, originally for explicitly describing the channel surface potential of undoped channel MOSFETs. The W function continued to be used in a growing number of occasions and situations related to MOSFET modeling. Among the many instances W has been used ever since for this purpose are: ultrathin body nanoscale devices, Double Gate and Surrounding Gate devices, polySi thin film transistors (TFTs), undoped and lightly- doped symmetric Double Gate devices, GAA undoped polySi nanowire devices, for FDSOI MOSFET parameter extraction, for charge and capacitance modeling in tunnel FETs, MOSFET modeling at deep cryogenic temperatures], in the Generalized EKV Compact MOSFET Model], to describe the charge density in Transition Metal Dichalcogenide FETs, and lately also for nanosheet transistors.
Adelmo Ortiz-Conde received the professional Electronics Engineer degree from Universidad Simón Bolívar (USB), Caracas, Venezuela, in 1979 and the M.E. and Ph.D. from the University of Florida, Gainesville, in 1982 and 1985, respectively. From 1979 to 1980, he served as an instructor in the Electronics Department at USB. In 1985, he joined the technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high voltage integrated circuits. In 1987, he returned to the Electronics Department at USB where he was promoted to Full Professor in 1995. He was on sabbatical leave at University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998. He also was on sabbatical leave at “Centro de Investigaciones y Estudios Avanzados” (CINVESTAV) National Polytechnic Institute (IPN), Mexico City, Mexico, from October 2000 to February 2001. He has coauthored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (2012 Springer reprint of the original 1st ed. 1998, http://dx.doi.org/10.1007/978-1-4615-5415-8 ), over 200 international technical journal and conference articles (including 22 invited review articles). His present research interests include the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is an EDS Distinguished Lecturer and the Chair of IEEE’s CAS/ED Venezuelan Chapter. He was editor of IEEE Electron Device Letters in the area of Silicon Devices and Technology from 2009 to 2018. He was the Region 9 Editor of IEEE EDS Newsletter from 2000 to 2005. He is a Member of the Editorial Advisory Board of various technical journals: Microelectronics and Reliability, “Universidad Ciencia y Tecnología” and “Revista Ingeniería UC”. He regularly serves as reviewer of several international journals and conferences. He was one of the founders of the first IEEE International Caracas Conference on Devices, Circuits, and Systems (ICCDCS) in 1995. In order to make it more international, this conference changed its name to “International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS)” in its sixth edition in 2006. Since 2019, this conference has been sponsored by the IEEE Electron Devices Society (EDS) under the name of “IEEE Latin America Electron Devices Conference (LAEDC)”.
3) Novel Applications of 2D Materials from AI/Memory Devices to 6G Switches to Wearable Sensors
Prof. Dr. Deji Akinwande, University of Texas – Austin
This talk will present our latest research adventures on 2D nanomaterials towards greater scientific understanding and advanced engineering applications. In particular, the talk will highlight our work on flexible electronics, zero-power devices, single-atom monolayer memory, non-volatile RF/5G/6G switches, and wearable tattoo sensors for mobile health. Non-volatile memory devices based on 2D materials are an application of defects and is a rapidly advancing field with rich physics that can be attributed to metal adsorption into vacancies. The memory devices can be used for neuromorphic computing and operate as switches up to 500GHz. Likewise, from a practical point, electronic tattoos based on graphene have ushered a new material platform that has highly desirable practical attributes including optical transparency, mechanical imperceptibility, and is the thinnest conductive electrode sensor that can be integrated on skin for physiological measurements including blood pressure monitoring. Much of these research achievements have been published in leading journals.
Deji Akinwande is an Endowed Chair Professor of Engineering at the University of Texas at Austin, and a Fellow of the IEEE, the MRS, the APS, and the AAS. His research focuses on 2D materials, pioneering device innovations from lab towards applications for which he is a Clarivate Highly Cited Researcher. He received the PhD degree from Stanford University in 2009. Prof. Akinwande has been honored with the 2018 Fulbright Specialist Award, 2017 Bessel-Humboldt Research Award, the U.S Presidential PECASE award, the inaugural Gordon Moore Inventor Fellow award, the inaugural IEEE Nano Geim and Novoselov Graphene Prize, the IEEE “Early Career Award” in Nanotechnology, the NSF CAREER award, several DoD Young Investigator awards, and was a past recipient of fellowships from the Kilby/TI, Ford Foundation, Alfred P. Sloan Foundation, 3M, and Stanford DARE Initiative. His research achievements have been featured by Nature news, Time and Forbes magazine, BBC, CNN, Discover magazine, Wall Street Journal, and many media outlets. He serves as an Editor ACS Nano and Nature NPJ 2D Materials & Applications, and on the editorial board for Science. He was the co-Chair of the Gordon Research Conference on 2D electronics, and was a past Chair of the 2018/2019 Device Research Conference (DRC), and the Nano-device sub-committee for the 2018 IEEE IEDM Conference. He co-authored a textbook on carbon nanotubes and graphene device physics by Cambridge University Press, and was recently a finalist for the Regents' Outstanding Teaching Award, the highest teaching award from the University of Texas System.
4) Modeling FinFETs, Nanowires and Nanosheets
Prof. Dr. Antonio Cerdeira Altuzarra, Solid State Electronics Section, Dep. of Electrical Engineering, Center of Research and Advanced Studies, Mexico City, Mexico
The transition from two-dimensional (2D) transistors to three-dimensional (3D) transistors at the beginning of the 21st century required the development of new models for 3D transistors. The work of developing models of semiconductor devices is a typical activity of the Academy, which our group followed, beginning the development of a new model for 3D FinFET devices, in 2006. These devices have a silicon fin, surrounded by three gates, two laterals and one on the top. The Si layer is narrow enough, creating a potential distribution across its thickness, where the potential at the center is different from zero. Considering this potential distribution and the fact that the Si layer is doped, lead to a transcendental equation for the distribution of the electric field from gate to gate, that has no direct analytical solution. In this presentation we will show an example of a compact, continuous and analytical model known as Symmetric Doped Double-Gate Model (SDDGM), where the indicate problems were solved. The model was complemented with variable mobility, the effects of short channel, leakage currents and dependence on ambient temperature. In addition, it was demonstrated that this model can be used to model also recent 3D structures, such as nanowires, nanosheets and stacked nanosheets. Validation of the using this model for these new devices will be shown. SDDGM was implemented in the circuit simulator SmartSPICE, using Verilog-A language. Even today, the development of more precise models, as well as complements for applying them to new devices, is an open topic for the Academy.
Prof. Antonio Cerdeira Altuzarra - He received the M.Sc. degree in physics from Moscow State University, Russia, in 1966 and the Ph.D. degree from the NW Leningrad Polytechnic Institute, Russia, in 1977. Since 1966, he has been engaged in research, teaching and development in the field of microelectronics, including design, technology, characterization, simulation and modeling. He has been Professor at the Faculty of Physics, 1966-1979 and Director of the Solid- State Electronics Research Laboratory, 1968-1979, at University of Havana; head of Research Department at INSAC in Cuba, 1979-1990, head of Microelectronic Department at International Center of Informatics in Moscow, 1990-1994, and since 1995 he is a Full Professor at the Section of Solid-State Electronics, Department of Electrical Engineering, Center of Research and Advanced Studies (CINVESTAV) in México City. He has also been head of 14 research and infrastructure projects; author, coauthor of more than 300 technical papers and 4 patents. His actual research interest is in the field of modeling and characterization of multigate nanometric MOSFETs and Thin-Film Transistors (TFT), including the non-linear behavior of devices and circuits. Prof. Cerdeira is a Life Senior Member of the IEEE and IEEE Electron Devices Society Distinguished Lecturer.
5) 2D semiconductor FET transistors: Characteristics, fabrication and modelling
Profa. Dra. Magali Estrada, Solid State Electronics Section, Dep. of Electrical Engineering, Center of Research and Advanced Studies, Mexico City, Mexico
The metal-oxide-semiconductor field effect transistor, where silicon is the semiconductor material, Si MOSFETs, and their successors FINFETs and multigates devices (nanowires, nanosheets, stacked devices, etc) are at present, the basic semiconductor device allowing the tremendous development reached by actual semiconductor industry to meet the requirements of data processing, artificial intelligence mobile devices and other techniques necessary for economic, social, and scientific development. To achieve the required demands, it has been necessary a constant reduction of the transistor size, which has the prediction of Moore´s Law, of duplicating the number of transistors in a chip every two-three year. This miniaturization process has had to overcome important problems related to parasitic effects present in bulk materials called short channel effects (SCEs). For example, as the channel length is reduced, the device current in the below threshold regime will increase, and so, the static power consumed. A detailed study of the electrostatic characteristics of FET devices, described by Poisson equation can be done, using the so-called characteristic channel length, defined as , where xs and xi are the width and thickness of the semiconductor layer and insulator, respectively, and ks, ki, their relative dielectric constants. λ can be reduced, by reducing the thickness of the semiconductor or the insulator layers, as well as, by increasing the relative dielectric constant of the insulator layer. However, in bulk 3D semiconductors, the reduction of xs, increases the threshold voltage VT., due to the increase of defects as dangling bonds and interface states at the interface of the semiconductor/dielectric. At the same time, mobility decreases as xs6 due to the increase in carrier scattering at the surface. In general, for ultrathin 3D FETs, the electrostatic control of carriers in the channel is reduced, while the leakage current increases. On the contrary, in a two-dimensional (2D) material, electrons can be naturally confined within a very thin channel formed by few monoatomic layers, where carriers can in principle uniformly controlled by the gate voltage, while the leakage current reduces. For the above reasons, during the last years, much work has been done regarding the possibility of using 2D semiconductors to overcome the above-mentioned limitations in further scaling of 3D semiconductor devices. In this talk, we will analyse some of these characteristics, as well as results obtained in fabricating 2D semiconductor FETs, using different methods. Finally, we will present some work done on modelling these new devices, already available and discuss challenges to overcome.
Dr. Magali Estrada is a Full professor at the Section of Solid-State Electronics at the Center of Research and Advances Studies, in Mexico City. Since 1966, she has been working in research and education, in the field of Solid-State Electronics, especially in device fabrication, characterization and modelling. She has been engaged with different types of semiconductor devices, Si MOSFETs, FinFETs, nanostructures, as well as TFTs, solar cells, and 2D FETs, with different semiconductor materials and structures. She is Life member and DL of the EDS/IEEE Society.
6) 3D millimeter-wave imaging and sensing with Si-based phased arrays, edge computing, and AI
Dr. Alberto Valdes Garcia, IBM Thomas J. Watson Research Center, USA
The use of millimeter-wave frequencies for 5G networks has been a primary contributor for transitioning Si-based phased array technology from R&D to real-world deployments. While the commercial use of millimeter-wave sensing so far has been dominated by low- cost, compact MIMO radars for automotive and industrial applications, the on-going wide deployment and advancement of Si-based phased arrays opens a new horizon of opportunities for sensing and event recognition. This talk will first cover the fundamentals and KPIs of 3D radar systems using phased arrays including associated key circuit design and packaging design techniques. Examples of such 3D radar systems at 28-GHz, 60- GHz and 94-GHz will be provided. Next, the presentation will describe how the full potential of such systems can be realized through synergistic co-design with algorithms and edge computing assets. Key examples of emerging applications based on these vertically integrated antennas-to-software/AI systems will be provided including multi- spectral imaging, 5G mmWave joint sensing and communications, and AI-based recognition of human gestures and concealed objects.
Dr. Alberto Valdes Garcia, Principal Research Scientist/Manager, IBM Thomas J. Watson Research Center Alberto Valdes-Garcia is currently a Principal Research Scientist and Manager of the RF Circuits and Systems Group at the IBM T. J. Watson Research Center. In his current role, he leads a multi-disciplinary team that investigates and develops technologies that bridge the gap between antennas and edge-compute-based AI, enabling new millimeter-wave systems and applications for imaging and communications. Dr. Valdes-Garcia received the Ph.D. degree in Electrical Engineering from Texas A&M University in 2006. He holds >130 issued US patents and has authored >100 peer-reviewed publications. Recent awards include the 2017 Lewis Winner Award for Outstanding Paper, presented by the IEEE International Solid-State Circuits Conference, and the 2017 IEEE Journal of Solid-State Circuits Best Paper Award. In 2013, he was selected by the National Academy of Engineering for its Frontiers of Engineering Symposium. He currently serves in the Inaugural Editorial Board of the IEEE Journal of Microwaves and was the Chair of the IEEE MTT-S Microwave and Millimeter-Wave Integrated Circuits Committee in 2020-2021. Dr. Valdes-Garcia is an IEEE Fellow since 2024, was inducted into the IBM Academy of Technology in 2015, and was recognized as an IBM Master Inventor in 2016, 2019, and 2022.