Welcome to Chip in Sampa 2026
São Paulo, SP, Brazil
August 24 to 28, 2026
The “Chip-in-Sampa 2026” is the most important microelectronics international event that takes place in Brazil. This event is held on August 24 to 28, 2026 in São Paulo, the Brazilian economic center, and its organization is led this year by the Laboratory of Integrated Systems (LSI), LSITEC and Polytechnic School of University of São Paulo (USP).
The Chip-in-Sampa 2026 is composed by six events:
In addition, there are Industrial Panel and many technical and administrative meetings. During the Opening and Closing sessions different Awards will be presented. All activities are focused on academic and industrial professionals, graduated and undergraduate students, allowing a fruitful meeting of the microelectronics community and contributing to the emergence of the next generation of Brazilian microelectronics researchers and professionals.
The different events organized within Chip-in-Sampa 2026 are sponsored by Brazilian Microelectronic Society (SBMicro) and Brazilian Computer Society (SBC) and co-sponsored by many international societies, such as: IEEE Electron Device Society (EDS), IEEE Circuits and Systems (CAS), IEEE Council on Electronic Design Automation (CEDA), IEEE Instrumentation & Measurement, Association for Computing Machinery (ACM), ACM-special interest group on design automation (SIGDA) and International Federation for Information Processing (ifip). A special thanks to the Brazilian sponsoring agencies CAPES, CNPq and FAPESP.
We would like to thank all the support from academic societies, from companies and from Brazilian agencies. We also would like to thank the Executive Committee, the Local Arrangements Committee, the reviewers and the authors of the manuscripts. Together, this was an enormous human effort that enabled the success of this conference. Thank you very much! We hope the microelectronics community enjoys Chip-in-Sampa 2026 and all activities that are carefully prepared for the audience.
Welcome to São Paulo
João Antonio Martino
Chip-in-Sampa 2026
General Chair
Keynote Speakers
Prof. Dr. Cor Claeys
Fellow IEEE, Fellow ECS
KU Leuven, Leuven, Belgium
Title: Research and Development Driving Advanced Semiconductor Devices Challenging the End of the Roadmap
Abstract
Short Bio
Semiconductor technology has known an exponential evolution in the last decades and is fully
integrated in our everyday life. The global semiconductor industry sales are expected to reach about US$ 600 billion in 2024. This could only be achieved by the implementation of novel materials, advanced design concepts and new transistor architectures. Research and development have focused on increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the
cost/function. Device architectures such as FinFETs, TFETs, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, Forksheet and CFET structures are investigated enabling System-on-Chip (SoC) applications. In addition, the huge progress achieved in silicon technology and the heterogenous integration of Ge and III-V technologies on a silicon platform enables the on-chip integration of building blocks with different functionality.
Depending on the required power output, maximum breakdown voltage and frequency performance there is completion between SiC and GaN based technologies for a variety of applications fields such as mobile communication, automotive, consumer products, etc. The main challenges related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects due to the lattice mismatch of the different materials.
Complex and dense SoC applications can be realized by 3D wafer stacking using Through-Silicon-Vias (TSV) for wafer-to-wafer bonding. The 3D integration results in a reduction of the RC product and interconnect length, a smaller form factor and enables vertical partitioning. Very promising results are also obtained for monolithic sequential 3D (S3D) processing based on the processing of different tiers on top of each other. Major trends in above mentioned process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He teaches several short courses in different parts of the world.
He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium”, “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”.
He also (co)authored 16 book chapters, over 1200 conference presentations and more than 1400 technical papers. He is editor/co-editor of 70 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award.
