Salvador Pinillos Gimenez
FEI University Center / PUC-SP / MTG2i Solutions LTDA
From Unconventional Gate Geometries to AI-Driven CMOS IC Design: A Decade of Innovation in Devices, Sensors, and the iMTGSPICE Framework
This invited talk presents a comprehensive overview of more than a decade of research on two synergistic fronts: I- the development and characterization of planar MOSFETs with non-conventional gate geometries; II- the design and application of iMTGSPICE, an AI-powered interactive evolutionary tool for the automated optimization of analog and radiofrequency CMOS integrated circuits (ICs).
On the device side, a family of innovative layout styles for MOSFETs is introduced, including the Diamond (hexagonal), Octagonal (OCTO), Fish, Ellipsoidal, Half-Diamond, and hybrid gate geometries, all implementable in standard planar CMOS and Silicon-On-Insulator (SOI) technologies without additional manufacturing cost. These unconventional geometries exploit physical effects not present in conventional rectangular-gate MOSFETs, namely the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), and the Deactivation of Parallel MOSFETs in the Bird’s Beak Regions (DEPAMBBRE) to deliver remarkable improvements in drain current, transconductance, analog figures of merit, ionizing radiation tolerance, and high-temperature operation. Experimental and numerical simulation results are presented for bulk and SOI technologies, covering digital, analog, and power MOSFET applications. Applications of these devices as sensors are also discussed, including the use of Fish MOSFETs as constructive elements in photovoltaic solar cells that generate longitudinal photocurrent, and their suitability for operation in harsh environments such as aerospace, nuclear, and biomedical systems.
On the design-tool side, iMTGSPICE is presented as an interactive evolutionary framework that integrates customized artificial intelligence algorithms, including genetic algorithms with Gaussian fitness functions, interactive evolutionary strategies guided by designer knowledge, and a customized Imperialist Competitive Algorithm, directly with SPICE-level circuit simulation. The tool enables simultaneous optimization of performance, robustness, and die area for analog CMOS building blocks, including Miller Operational Transconductance Amplifiers (OTAs), cascaded OTAs, and Low Noise Amplifiers (LNAs). Key results demonstrate significant reductions in design-and-optimization cycle time alongside improvements in electrical performance across multiple technology nodes.
Finally, the co-design synergy between non-conventional MOSFET layout styles and iMTGSPICE is highlighted: by combining Diamond layout-style transistors with AI-driven optimization, it is possible to simultaneously boost the electrical performance and robustness of CMOS analog ICs while substantially reducing die area — a result unachievable with either approach alone. This integrated ecosystem serves as the technological foundation for MTG2i Solutions, the first startup of FEI University Center, supported by FAPESP under the PIPE program.
SALVADOR PINILLOS GIMINEZ. From 2009 to 2015, he held the Productivity Scholarship in Technological Development and Innovative Extension (DT). Later, starting in 2017, I became a recipient of the CNPq Research Productivity Scholarship – PQ Level 2. My research is concentrated on innovative layout designs for semiconductor devices and sensors, particularly in their application to digital, analog, and radio frequency (RF) CMOS integrated circuits (ICs). Additionally, in the realm of Evolutionary Electronics, we create computational tools for the robust design and optimization of analog and RF CMOS ICs. These tools integrate heuristic optimization methodologies from Artificial Intelligence (AI) with the insights of human designers (Human Intelligence, HI), which substantially shortens the design and optimization cycle of these CMOS ICs. This work led to the establishment of the first start-up at FEI University Center, backed by FAPESP through the PIPE phase 1 and PIPE phase 2 programs (MTG2i Solutions LTDA). At FEI University Center, I oversee the Microcontrollers course for undergraduates and the Analog Circuits and Systems and Special Topics in Analog Integrated Circuit Design courses for graduate students. I also teach at the Pontifical Catholic University (PUC) of São Paulo, where I am involved in Cyberphysical Systems Engineering and supervise scientific initiation projects. For further details on my academic and professional journey, please visit my Lattes CV at http://lattes.cnpq.br/1372738121180882.