Universidad Simon Bolivar, Venezuela
IEEE Electron Device Society (EDS) – Distinguished Lecturer Presentation
Title: Evolution of semiconductor devices from its conception to our present.
We review the origins, evolution, recent developments and present status of MOSFET, which has been the dominant semiconductor device in microelectronics applications for more than 3 decades. The conceptual invention of MOSFET, by Lilienfeld in 1928, inspired Bardeen and Brattain to fabricate the first point contact transistor in 1947, at Bell Labs. This achievement motivated Shockley, also from Bell Labs, to invent the bipolar transistor in 1948. Bardeen, Brattain and Shockley received the Nobel Prize in 1956. After solving oxide reliability problems, the MOSFET was fabricated in 1960 by Kahng and Atalla. The invention of CMOS, by Wanlass and Sah in 1963, made the MOSFET to be the most commonly used device in microelectronic. The transistors have been miniaturized for more than fifty years, following Moore’s Law from 1965, and they are now approaching its final limits in the nanometer regime. Recent innovations, as strained silicon and high-k metal gate are being used in modern MOSFETs. New device designs as FinFETS, Nanowire and Nanosheet are now being fabricated.
Adelmo Ortiz-Conde received the professional Electronics Engineer degree from Universidad Simón Bolívar (USB), Caracas, Venezuela, in 1979 and the M.E. and Ph.D. from the University of Florida, Gainesville, in 1982 and 1985, respectively. From 1979 to 1980, he served as an instructor in the Electronics Department at USB. In 1985, he joined the technical Staff of Bell Laboratories, Reading, PA, where he was engaged in the development of high voltage integrated circuits. In 1987, he returned to the Electronics Department at USB where he was promoted to Full Professor in 1995. He was on sabbatical leave at University of Central Florida (UCF), Orlando, from January to August 1994, and again from July to December 1998. He also was on sabbatical leave at “Centro de Investigaciones y Estudios Avanzados” (CINVESTAV) National Polytechnic Institute (IPN), Mexico City, Mexico, from October 2000 to February 2001. He has coauthored one textbook, Analysis and Design of MOSFETs: Modeling, Simulation and Parameter Extraction (2012 Springer reprint of the original 1st ed. 1998, http://dx.doi.org/10.1007/978-1-4615-5415-8 ), over 160 international technical journal and conference articles (including 20 invited review articles). His present research interests include the modeling and parameter extraction of semiconductor devices. Dr. Ortiz-Conde is an EDS Distinguished Lecturer and the Chair of IEEE’s CAS/ED Venezuelan Chapter. He was editor of IEEE Electron Device Letters in the area of Silicon Devices and Technology from 2009 to 2018. He was the Region 9 Editor of IEEE EDS Newsletter from 2000 to 2005. He is a Member of the Editorial Advisory Board of various technical journals: Microelectronics and Reliability, “Universidad Ciencia y Tecnología” and “Revista Ingeniería UC”. He regularly serves as reviewer of several international journals and he was the General Chairperson of the first IEEE International Caribbean Conference on Devices, Circuits, and Systems (ICCDCS) in 1995, Technical Chairperson of the second, fourth and fifth editions of this conference in 1998, 2002 and 2004 respectively, and the Chairperson of the Steering Committee in 2000.
Federal University of Rio Grande do Sul (UFRGS), Brazil
IEEE Electron Device Society (EDS) – Distinguished Lecturer Presentation
Title: Unifying the Modeling of Charge Trapping in RTN, 1/f Noise and BTI.
In this presentation we discuss how charge trapping produces BTI, RTN and low- frequency noise, detailing unified statistical modeling. Modeling is based on discrete device physics quantities, which cause variability in the electrical behavior of MOSFETs. It allows for the derivation of analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI using a single modeling framework. The area scaling of threshold voltage variance is detailed and discussed, supporting designers in transistor sizing towards a more reliable design. Parameter extraction is addressed, showing that it is possible to extract model parameters without having to characterize individual trap step heights (individual trap amplitudes). It is also discussed how charge trapping produces timing jitter in digital circuits and phase noise in analog circuits.
Gilson Wirth received the B.S.E.E and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund, Dortmund, Germany. He is currently a professor at the Electrical Eng. Depart. at Univ. Federal do Rio Grande do Sul - UFRGS (since January 2007). From July 2002 to December 2006 he was professor and head of the Computer Engineering Department, Univ. Estadual do Rio Grande do Sul - UERGS. His current research work focuses on modeling and electrical stimulation of charge trapping in the context of Bias Temperature Instability (BTI), Low-Frequency Noise (1/f and RTN) and Hot Carrier Injection (HCI). He has also worked on ionizing radiation effects (TID and SET/SEU) on semiconductor devices. He focuses on collaborative work with academia and industry. He has stablished successful collaborative work with different companies and research groups in Europe, North and South America, and China. Has signed NDA with the following companies: Intel, Texas Instruments, NXP Semiconductors and Infineon Technologies. He is currently a Distinguished Lecturer of the IEEE Electron Devices Society. He also was a distinguished lecturer of the IEEE Circuits and Systems Society (term 2010- 2011). An updated list of publications may be found at http://lattes.cnpq.br/1745194055679908 Or https://publons.com/researcher/3063393/gilson-wirth/
University of Padova, Italy
IEEE Solid State Circuits (SSCS) – Distinguished Lecturer Presentation
Title: High Resolution Radar Imaging for Breast Cancer Detection: Trends and Challenges
Over the last few years, a significant growth of the research involving the use of microwaves to image the human body has been taking place. Among the many examples of ongoing research, the use of microwaves for breast cancer diagnostic imaging has seen an increasing interest. Ultra wideband microwave radar imaging can effectively complement conventional diagnostic techniques, e.g. X‐ray, MRI, ultrasound, yielding higher sensibility and specificity, lower cost, and smaller size, hence emerging as an enabling technology for mass screening programs. Ultra wideband radars can be realized in different technologies, discrete or fully integrated. This talk investigates the typical system and circuit-level challenges of such radars, and discusses some implementation examples. The talk presents innovative circuit solutions addressing the challenges set by the ultra-wideband frequency range of operation of the radar transceiver. Due to their broadband operation, such design techniques may find application in other wideband systems.
Andrea Bevilacqua received the Laurea and Ph.D. degrees in electronics engineering from the University of Padova, Padova, Italy, in 2000, and 2004, respectively. From 2005 to 2015, he was an Assistant Professor with the Department of Information Engineering, University of Padova, where he is now an Associate Professor. His current research interests include the design of analog and RF/microwave integrated circuits and the analysis of wireless communication systems, radars, and dcdc converters. He is author or co-author of more than 90 technical papers, and he holds 5 patents. Dr. Bevilacqua is a member of the ITPC of IEEE ISSCC. He served in the TPC of IEEE ESSCIRC from 2007 to 2019, and was TPC Co-Chair of IEEE ESSCIRC 2014. He was a member of the TPC of IEEE ICUWB from 2008 to 2010. He was an Associate Editor of the IEEE Transactions of Circuits and Systems II from 2011 to 2013 and was nominated Best Associate Editor for the IEEE Transactions of Circuits and Systems II for 2012 to 2013. He served as a Guest Editor for the special issue of the IEEE Journal of Solid-State Circuits dedicated to ESSCIRC 2017.
Federal University of Rio Grande do Norte (UFRN), Brazil
Title: Thermoresistive Sensors, Applications and Electrical Equivalence Principle.
Thermoresistive sensors find several applications beyond temperature measurement.
These include applications for measurement of fluid speed, incident radiation (solar,
infrared and microwave radiation), AC power, gas detection, acceleration and gyroscopes.
Sensors architectures, i.e. the analog front-end that provides excitation for generating the
measurement signal, play an important role in the measurement system performance, like
response time, linearity, sensitivity, power, among others. In architectures employing the
electrical equivalence principle, the sensor operates near a constant temperature, in a
feedback control configuration, where variations of the measurand are substituted by
equivalent variations of the electrical power delivered to the sensor. Among several sensor
architectures, those employing the electrical equivalence principle provide best response
time and can mitigate a sensor nonlinear temperature-resistance relationship.
Nevertheless, these architectures still present some shortcomings, which motivate
research for improvements and for new architectures and techniques, evidencing the
timeliness of the topic.
This Lecture will cover:
• The basics of thermoresistive sensors and characteristics.
• Principle of operation and measurement.
• Architectures employing electrical equivalence principle.
• Concluding remarks showing some possible directions for the advance of the state- of-the-art on the theme.
Sebastian Yuri Cavalcanti Catunda graduated in electrical engineering from the Federal University of Paraíba (1993), obtained a master's degree from the Federal University of Paraíba (1996) and a doctorate in electrical engineering from the Federal University of Campina Grande (2000) and École Nationale Supérieure des Télécommunications - ENST, Paris. He was a professor in the Department of Electricity Engineering at the Federal University of Maranhão (UFMA) from 1998 to 2011. At UFMA, he coordinated the Graduate Program in Electricity Engineering from 2005 to 2011. In 2011, he joined the Federal University of Rio Grande do Norte (UFRN), in Natal, where he is currently full professor at the Department of Computer and Automation Engineering. He has been a member of NAMITEC (currently INCT-NAMITEC) since 2006. At the Brazilian Automation Society (SBA), he founded the Instrumentation Committee in 2007 and was the Society’s institutional relations secretary from 2015 to 2016. He has been a senior member of IEEE since 2013. Founded in 2013 and chaired until 2017, the IEEE IMS / CASS Chapter of the Bahia section. In 2016, he founded the International Symposium on Instrumentation Systems, Circuits, and Transducers (INSCIT), which is supported by the Brazilian Microelectronics Society and technically sponsored by the IEEE Instrumentation and Measurement Society (IMS). He was elected to the IEEE IMS Administrative Committee for the period 2018-2021 and Vice President for IEEE IMS Conferences in 2021. He is a level 1D researcher in the Microelectronics area of CNPq and was a member of its Advisory Board from 2012 to 2018. His research interests focus on instrumentation and microelectronics, including the topics of sensors, analog and mixed circuits, embedded systems and data acquisition systems.
University of São Paulo (USP), Brazil
Title: Chemical Sensors for Detection of Hydrogen and Acetylene
This presentation is focused on the fabrication process of chemioresistors for hydrogen detection and potentiostatic cells with three electrodes for acetylene detection for environmental monitoring applications. Nowadays, there is an increasing interest to detect hydrogen and hydrocarbons that can be found in marine and atmospheric environments, and in the process of oil production. It will be shown that chemical sensors can be used for gas detection of gas leaks in clean rooms, leak detection in gas compressors, fail monitoring of high-voltage transformers and ripening process of fruits.
Sebastião Gomes dos Santos Filho was born in São Paulo, Brazil, in 1962. He received the Electrical Engineering, M.Sc., and Ph.D. degrees from the Polytechnic School, University of São Paulo, São Paulo, Brazil, in 1984, 1988, and 1996, respectively. In 1985, he joined the Laboratory of Integrated Systems of the Polytechnic School of the University of São Paulo (LSI/EPUSP) as researcher in microelectronics and graduate student. Since 2008, he is full professor at the Electronics Systems Department of the Polytechnic School of the University of São Paulo (EPUSP). He was Coordinator of the Graduate Program in Electrical Engineering of the University of São Paulo from 2011 to 2013 and currently he is Head of the Electronics Systems Department (EPUSP) since 2016. He has authored or coauthored more than 200 papers published in journals or conferences and he has supervised 18 PhD dissertations amd 23 MSc Theses. His main research interests concern surfaces and interfaces engineering, chemical sensors, solar cells, R&D of chemical cleaning for silicon wafers, high-k dielectrics, electrochemical deposition and nanostructured systems.
FEI University Center, Brazil
Title: Impact of Using Non-standard Layout Styles for MOSFETs
This presentation describes the impacts in the electrical behaviors of different non- standard layout styles for MOSFETs. The generated effects by the non-standard layout styles for MOSFETs (LCE, PAMDLE and DEPAMBBRE) are discussed in this presentation. These effects are capable of reducing their gate areas, improving the electrical performance of MOSFETs, mainly focusing on the analog Integrated Circuits (ICs) applications, and increasing their robustness when they are operating in ionizing radiation environment (space and nuclear applications), in comparison to the typical layout style (rectangular gate) for MOSFETs, regarding that they have the same gate area and under the same bias conditions. A simple analytical model was developed for the drain current of these innovative layout styles for MOSFETs. Besides, it was implemented a methodology to simulate in SPICE these MOSFETs layouted with non-standard layout styles, aiming to use them to implement analog and digital ICs.
Salvador Pinillos Gimenez (Senior Member, IEEE) received the graduation degree in electrical engineering from the Faculty of Electrical Engineering, UMC, in 1984, and the master’s degree in electrical engineering from the Microelectronics Laboratory, Polytechnic School, University of São Paulo, in 1990, and the Doctoral degree in electrical engineering from the Integrated Systems Laboratory, University of São Paulo, in 2004. He is currently a Full Professor with the University Center of FEI and an Assistant Professor with the Pontifical Catholic University of São Paulo. He has experience in the field of electrical engineering, with an emphasis on microelectronics (design, simulation, and characterization of new SOI MOSFET devices, including power, and SOI CMOS analog and digital integrated circuits. Nucleus is the area of evolutionary electronics applied to integrated circuits design analogue and digital) and in the area of microcontrollers [Author of Books: Microcontrollers 8051 (Prentice Hall/Pearson Education, in 2002), and Microcontrollers 8051–Theory and Practice (Editora Erica, in 2010)]. He holds several patents, including Diamond SOI MOSFET, Wave SOI MOSFET, Poligonal SOI MOSFET, Fish (FISH) MOSFET, and Gastric Electrostimulation System. He has authored the book “Power Electronics—AC/DC Energy Converters–Theory, Practice and Simulation,” in 2011, "Layout Techniques for MOSFETs”, in 2016 (Morgan and Claypool Publishers) and "8051 Microcontrollers”, in 2018 (Springer). He has professional experience with DIMEP SA, as a Project Development Engineer from 1987 to 1993, as an Eng. De Project Development with TRACECOM, in 1993 and as a Component and Supplier Development Engineer/Quality and Productivity Coordinator with FORD Ind. E Com.–Electronic Division from 1994 to 1999.(Based on document published on 26 October 2020).
Federal University of Minas Gerais (UFMG), Brazil
Title: Analog IC design in scaled CMOS technology
CMOS technology scales by a factor of two every four years guided by Moore's Law. In sub-micron devices, short-channel effects lead to threshold voltage shifting, increased noise, and mismatch. Low voltage supply is a necessity in scaled technologies. Low VDD bounds physical 2nd-order effects, which affect the reliability and the robustness. The analog IC designer must look for new design strategies and topologies to improve the circuit's performance in nanometer scaled CMOS technology. I will first make a compact overview of the challenges imposed by the use of scaled technologies in analog IC design. Then, I will present some examples of analog circuits designed in 65nm CMOS technology, to demonstrate that it is possible to develop circuit solutions in order to achieve the same performance.
Hugo Daniel Hernandez Herrera is a researcher in Mixed-Signal Integrated Circuits Design. He was an IC designer at LSITEC and DFCHIP (Brazil) where worked for 8 years, and Pos-doc of the Universidad de Sao Paulo in collaboration with the CERN (Switzerland) as analog IC designer in the SAMPA ASIC project. He is currently Professor of the Department of Electrical Engineering of the Federal University of Minas Gerais (UFMG). He holds a degree in Electronic Engineering from the Industrial University of Santander (Colombia) in 2005, M.S. and Ph.D. degree in Electrical Engineering from Polytechnic School of the University of São Paulo (Brazil) in 2008 and 2015, respectively.
University of California, Berkeley, USA
IEEE Electron Device Society (EDS) – Distinguished Lecturer Presentation
Title: Adaptable Electronics
We are embarking on a future where ubiquitous electronics deployable anywhere and
seamlessly connected will be reality. While integration of minds from different spectrums of
various disciplines will be the key to facilitate that, integration of the actual physical
electronic systems will become more and more important beyond its current premises in
In this talk, therefore I’ll be sharing some of my perspectives about adaptable electronics. The electronics which can adapt themselves to any changing environment. We will use a concept of multi-dimensional Integrated Circuits (MD-IC) which can assume different shapes and sizes as well as shape changing lateral circuitry to adapt to a variety of circumstantial need will be discussed with finite element modeling and practical development. I would also shows how they can be used to a variety of applications ranging from security to environmental monitoring to healthcare.
Mustafa (PhD, ECE, UT Austin, Dec 2005) is a Professor of EECS, UC Berkeley. He was a Founding Professor of Electrical and Computer Engineering, KAUST from 2009 to 2020. He was Program Manager in SEMATECH (2008-2009) and Process Integration Lead for 22 nm node FinFET CMOS in Texas Instruments (2006-2008). His research is focused on futuristic electronics which has received support from DARPA, Boeing, Lockheed Martin, GSK-Novartis, Saudi ARAMCO and SABIC. He has authored 450+ research papers and patents. He is a Fellow of IEEE, American Physical Society (APS) and Institute of Physics (UK), a distinguished lecturer of IEEE Electron Devices Society, and an Editor of IEEE T-ED. His research has been extensively highlighted by international media (CNN, Fox News, MSNBC, Washington Post, WSJ, National Geographic, Forbes, IEEE Spectrum, etc.) including being featured by Scientific American as one of the top 10 world changing ideas in 2014. He has received more than 45 international awards including Best Innovation Award in CES 2020, Edison Award 2020, UT Austin Outstanding Young Alumni Award 2015, IEEE Outstanding Individual Achievement Award 2016, etc. He is also the host of popular IEEE EDS Podcast Series with EDS Luminaries.
Universitat Rovira i Virgili, Espanha
IEEE Electron Device Society (EDS) – Distinguished Lecturer Presentation
Title: Compact modeling of organic and amorphous oxide TFTs from 150 to 350K
We review the physics and modeling of Organic Thin-Film Transistors (OTFTs) and Amorphous Oxide Semiconductors Thin-Film Transistors ( AOS TFTs). We analyze the electrostatic and charge transport mechanisms in these devices. We demonstrate that compact OTFTs and AOS TFTs models can be developed by using analytical approximate solutions of Poisson's equation considering exponential Density of States (DOS) and on a transport model based on the combination of carrier hopping between localized states with drift current of free carriers. The resulting field-effect mobility expressions are power laws of the gate voltage overdrive. Analytical expressions are developed from the deep subthreshold regime to the well above threshold one. Besides, we present direct methods to extract model parameters. We show that most key parameters are extracted applying an integral operator to the measured transfer characteristics. We analyze drain current characteristics from 150K to 350K and show the temperature dependences of the extracted parameters. We also present capacitance modeling frameworks for OTFTs and AOS TFTs which are consistent with the developed drain current models. The modeled C- V characteristics are successfully validated by comparison with experimental data and TCAD simulations at different temperatures.
Benjamin Iñiguez obtained the Ph D in Physics in 1996 from the Universitat de les Illes Balears (UIB). In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering of the Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February 2010 he became Full Professor at URV. He obtained the Distinction from the Catalan Government for the Promotion of University Research in 2004 and the ICREA Academia Award (ICREA Institute) in 2009 and 2014. He led or is leading two research projects funded by the European Union. He has supervised 14 Ph D students, and co-supervised one more. He has published more than 170 research papers in international journals and more than 160 abstracts in proceedings of conferences. He was elevated to the grade of IEEE Fellow in 2019. His main research interest is the compact modeling of emerging semiconductor devices, in particular nanoscale Multi-Gate MOSFETs GaN HEMTs, and organic and oxide TFTs