XII Workshop on Semiconductors and Micro & Nano Technology


Seminatec 2017 Proceedings

Número ISBN: 978-85-86686-96-2
Título: Seminatec 2017 - XII Workshop on semiconductions and micro & nano technology


Organizers, Program and all papers: Link to download



First Day (April 27th)

 Second Day (April 28th)

08:30 - 09:10

Registration and Opening



 

Session I – Chair: João Antonio Martino

 

Session IV – Chair: Jacobus W. Swart, Marcelo A. Pavanello and Wilhelmus A. M. Van Noije

09:10 - 10:00

Dr. Cor Claeys, KUL/Imec, Belgium.

Material and Device Challenges for the End of the Roadmap CMOS Technologies

09:10 - 10:00

Dr. Héctor J. De Los Santos, NanoMENS Research, CA, USA.

NanoMEMS: Enabling the Internet of Things

10:10 - 11:00

Dr. Enrico Sangiorgi, Bologna University, Italy.

Do much with very little: micropower management for energy harvesting applications

10:10 - 11:00

Dr. Wladyslaw Grabinski, MOS-AK Association (EU)

FOSS TCAD/EDA tools for semiconductor device modeling

11:10 - 12:00

Dr. Bodgan Cretu, CAEN University, France

Low frequency noise as a diagnostic tool in advanced MOSFET technologies

11:10 - 12:00

Dr. Pieter Harpe, Eindhoven University of Technology, Hollande

Ultra low-power analog front-end design

12:00 - 14:00

Lunch

12:00 - 14:00

Lunch

 

Session II – Chair: Nilton Itiro Morimoto

 

Session V – Chair: Nilton Itiro Morimoto

14:00 - 14:30

Brasil Componentes – Alex Melo

Brasil Componentes – Uma empresa 100% nacional inserida no cenário de semicondutores

14:00 - 14:30

SMART – Luis Esteves/Cleber Figueira

Semiconductor Devices - Hardware for Future

14:30 - 15:00

Keysigth - Mauricio Kobayashi

Desafios e soluções de teste para caracterização de novos materiais

14:30 - 15:00

UNITEC – Edelweis/Ciro

Visão de mercado e desafios tecnológicos da indústria nacional de semicondutores.

15:00 - 15:30

CEITEC - Eric Fabris 

Perspectivas e Cenário Atual

15:00 - 15:30

HT Micron – Giovani Pesenti

HT Micron, tecnologia em encapsulamento e teste de semicondutores –

 

Session III – Chair: Paula G. Der Agopian

 

 

15:30 - 16:30

Flash Presentations (2 minutes/each)

15:30 - 16:00

Closing Remarks (and best papers awards) – João Antonio Martino   

16:30  - 18:00

Poster / Cocktail

 

 



 

Invited Speakers

Cor Claeys

KULeuven/Imec/Belgium

 

 Material and Device Challenges for the End of the Roadmap CMOS Technologies

Abstract:

 Advanced CMOS devices are driven by minimum device geometry, performance enhancement, cost issues and a low power consumption. This is achieved by optimizing process modules, introduction of new materials and modified device concepts. The implementation of stress engineering, ultra-shallow junctions, high-k gate-stacks with EOTs below 1 nm, optimization of process sequences (e.g. gate-first versus replacement gate or gate-last), raised source/drain for resistance control, use of high-mobility materials etc. is extensively studied.

 Improved drive currents and electrostatic control trigger the exploration of Multi-gate devices (MuGFETs). For scaled-down technologies, FD technologies with ultra-thin body and buried oxide (UTBB SOI) have demonstrated their strong potential down to the 10 nm mode. At those dimensions there exists a strong competition between planar UTBB SOI and bulk FinFETs. Tunnel-FETs (TFETs), relying on band-to-band-tunneling and allowing the achievement of steep subthreshold swings are studied. Both horizontal and vertical TFET approaches are emerging as post-CMOS alternatives. Further scaling leads to gate-all-around and nanowire devices.

 Optimized epitaxial growth techniques resulted in the fabrication of Ge (p-channel), III-V (n-channel) or hybrid Ge/III-V devices on a Si substrate. These high mobility materials are also implemented in TFET and nanowire structures. Heterogeneous integration enables the realization of System-on-Chip (SoC) applications which will play an important role in the era of Internet of Things (IoT).

The first part of the presentation briefly addresses and highlights challenges of some key process modules such as optical lithography, high-k gate dielectrics, strain engineering, hetero-epitaxial growth, contact technology etc.

The second part will focus on future device structures such as TFETs, nanowires and 3D integration in general. Reflections will also be given on present-day hot topics such as 2D material and devices, spintronics and quantum computing.

Biography:

 Cor Claeys received the Ph.D. degree from KU Leuven in Belgium, where he is Professor since 1990. At imec he was Director of Advanced Semiconductor Technologies responsible for strategic relations. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering and material characterization. He co-edited a book on Low Temperature Electronics and Germanium-Based Technologies: From Materials to Devices and wrote monographs on Radiation Effects in Advanced Semiconductor Materials and Devices, Fundamental and Technological Aspects of Extended Defects in Germanium and recently Random Telegraph Signals in Semiconductor Devices. Two of these books have been translated in Chinese. He authored and coauthored 14 book chapters, over 1100 conference presentations and more than 1300 technical papers. He is also editor or co-editor of 60 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was the Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, an elected Board of Governors Member of the Electron Devices Society and the EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009. He was as Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and in 2013 he received the IEEE EDS Distinguished Service Award.

Within the Electrochemical Society, he was the Chair of the Electronics & Photonics Division from 2001 to 2003. In 2004, he received the Electronics & Photonics Division Award.

In 2016 he received the Semi China Special Recognition Award for his outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).

 

 

Enrico Sangiorgi

Bologna University, Italy

 

Do much with very little: micropower management for energy harvesting applications

 

Abstract:

As the vision of the Internet-of-Things progressively takes shape and every day objects become smart and connected, new miniature power solutions are required. Energy available in the environment in forms like light, heat, vibration and electromagnetic waves can be captured and converted into electrical form. However, the feasibility of energy harvesting supplies is strongly determined by the efficiency of the associated power management electronics. In order to deal with the typical extremely low power levels, down to few µW, specific trade-offs and design techniques are required. In this context, microelectronics can be a driving technology towards the successful exploitation of such extremely low levels of power.
This lecture will discuss about the main power conversion techniques for different types of energy transducers with a focus on trade-offs between efficiency and internal consumption, and will analyze recent trends in the development of integrated power conversion and management electronics. Finally, case studies consisting in micro-/nano-power circuit implementations will be proposed.

 

Biography:

Enrico Sangiorgi received the Laurea degree from the University of Bologna in 1979. He has been a Visiting Scientist at Stanford University and Bell Laboratories.

He is currently Vice Rector at the University of Bologna. He has been Editor of Electron Device Letters for 15 years, on the editorial board for the Transactions on Electron Devices and Journal of Photo-Voltaics and he is currently Editor of the JEDS. His research covers the physics, characterization, modeling, and fabrication of solid-state devices and integrated circuits. He has been working on several aspects of device scaling, its technological, physical, and functional limits, as well as device reliability.

Enrico Sangiorgi EDS services include: Distinguished Lecturer (2004), Fellow (2005), member of the following Committees: Fellow, Cledo Brunetti, Educational Award, TCAD. Enrico Sangiorgi coauthored more than 250 papers that received so far more than 2,400 citations.

 

 


 

Bogdan Cretu

CAEN University, France

 

 

Low frequency noise as a diagnostic tool in advanced MOSFET technologies

Abstract:

In order to meet the International Technology Roadmap for Semiconductors (ITRS) specifications in terms of Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) downscaling, new materials, designs and structures are necessary. Multi-gate devices as UTBOXs, FinFETs and Gate All Around Nanowire FETs are known for their good electrostatic performances and their compatibility with CMOS processes as a continuation of Moores law. The study of low-frequency noise provides informations on both applications and process optimization, since it allows to go back to the physical sources of the fluctuations and to better understand certain physical phenomena present in the MOS transistors. The low frequency noise measurements can be used as a non-destructive device characterization tool in order to evaluate the quality of the silicon/dielectric interface and of the silicon film of advanced transistors. The low frequency noise studies effectuated in advanced devices (FinFETs, UTBOX, GAA NWFETs) have provided information on the interface traps, on the implantation and/or dry-etching induced traps, and were correlated with the technological characteristics of MOSFETs. Low frequency noise measurements may also be used in order to give additional input on the origin of some unusual behaviour observed in the output transfer characteristics

Biography:

Bogdan Cretu received the Bachelors degree in Physics from University Al.I.Cuza, Iasi, Romania in 1998. He received the M.Sc (1999) and the PhD (2003) in Physics of Semiconductors from the National Polytechnic Institute, Grenoble (INPG), France. In 2003 he joined the National Graduate School of Engineering & Research Centre (ENSICAEN) as Associate Professor and the GREYC laboratory for its research activities. He is author or co_author of 25 publications in international journals with reading committee and 42 international conferences with reading committee and proceedings. He was member of the organization committee of the International Conference on Noise and Fluctuations (ICNF2013). He was the French coordinator of two projects "Flemish Tournesol" of the Partnerships Hubert Curien (PHC) of Campus France (2008/2009 and 2012/2013), in collaboration with imec (Interuniversity MicroElectronics Center, Leuven, Belgium), focused on the study of the carrier transport phenomena and of the low frequency noise as a function of temperature in nanoscale transistors on SOI substrates and nanofilms. His main interests are in general the device physics, in particular low-temperature operation, electrical characterization and semi_analytical modelling of low frequency noise in advanced semiconductor devices.

 

 

 

 

 

Hector J. De Los Santos

NanoMENS Research, CA, USA.

 

NanoMEMS: Enabling the Internet of Things

Abstract:

NanoMEMS exploits the convergence between nanotechnology and microelectromechanical systems (MEMS) brought about by advances in the ability to fabricate nanometer-scale electronic and mechanical device structures. While the Nano aspect of this field is still in its early stages, and is not expected to reach maturity until well into the 21st century, its MEMS aspect is a topic of much current and near-term impact in, for instance, inertial sensing, biomedicine, optical, RF/Wireless communications, and energy harvesting. In this context, we will begin this talk by discussing the fundamentals of NanoMEMS, in particular, as it relates to its most speculative and futuristic paradigms and applications, and then will focus on emerging applications that are poised to enable the exploding Internet of Things (IoT) paradigm.

Biography:

Héctor De Los Santos received the Ph.D. degree from the School of Electrical Engineering, Purdue University, West Lafayette, IN, in 1989. Prior to founding NanoMEMS in 2002, he spent two years as Principal Scientist at Coventor, Inc., Irvine, CA, and eleven years at Hughes Space and Communications Company, Los Angeles, CA, where he served as Principal Investigator and Director of the Future Enabling Technologies IR&D Program. Under this program he pursued research in the areas of RF MEMS, Quantum Functional Devices and Circuits, and Photonic Bandgap Devices and Circuits. He holds over 30 US and European patents, and is author of bestseller textbooks, including Introduction to Microelectromechanical (MEM) Microwave Systems (1999), now in Artech House' IPF¨ (In-Print-Forever¨) series, RF MEMS Circuit Design for Wireless Communications (2001), and Principles and Applications of NanoMEMS Physics (Springer, 2005). His most recent book is Radio Systems Engineering: A Tutorial Approach (2014)

            Dr. De Los Santos is a member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. From 2001-2003 he lectured worldwide as an IEEE Distinguished Lecturer of the Microwave Theory and Techniques Society. His current research interests include, discovery, conception, theory, physics, computational modeling, simulation, analysis, design and applications of devices and circuits enabled by exploiting physical phenomena occurring down to nanometer length scales, including, plasmonics, photonic crystals, RF MEMS, and mechanical systems in the quantum regime.     The German Research Foundation (DFG) awarded him a Mercator Visiting Professorship, as a result of which he spent the 2010Ð2011 academic year at the Institute for High-Frequency Technology and Electronics (IHE), Karlsruhe Institute of Technology/University of Karlsruhe(TH), Karlsruhe, Germany, where his activities included conducting research on his DFG-funded project "Nanoelectromechanical Interferometric Tuning with Non-Equilibrium Cooling for Microwave and mm-Wave Electronics" and developing and teaching the courses  "Modern Radio Systems Engineering" and "NanoMEMS in High-Frequency Technology and Electronics." He is an IEEE Fellow.


 

Wladyslaw Grabinski,

MOS-AK Association (EU)

 

 

FOSS TCAD/EDA tools for semiconductor device modeling

Abstract:

Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

Biography:

Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH ZŸrich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now an consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also authored or coauthored more than 50 papers. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of the IEEE EDS Compact Modeling Technical Committee, organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He also serves as European representative for the ITRS Modeling and Simulation working group. He is a Member At Large of Swiss IEEE ExCom and also supports the EPFL IEEE Student Branch acting as its Interim Branch Mentor. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

 

 

Pieter Harpe

Eindhoven University of Technology, Hollande

 

 

Ultra low-power analog front-end design

Abstract:

This talk, based on a recent publication at ISSCC 2015, discusses the design of a nano-power analog front-end including pre-amplification and analog-to-digital conversion. It starts with fundamentals on power-efficiency in analog and mixed-signal circuits. It also describes considerations in terms of low-voltage operation and PVT reliability. After that, the presentation discusses one complete system implementation in more detail, including the amplifier, ADC, biasing stages and clock generation.

 

Biography:

Pieter Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands. In 2008, he joined Holst Centre / imec where he worked on low-power ADCs. In April 2011, he joined Eindhoven University of Technology as assistant professor on low-power mixed-signal circuits. His main interests include power-efficient and reconfigurable data converters and low-power analog design. He is a TPC member for ISSCC, ESSCIRC and AACD, and serves as Distinguished Lecturer for the IEEE Solid-State Circuits Society. He is recipient of the IEEE ISSCC 2015 Distinguished Technical Paper Award



Poster Session


Process and Materials


  1. Design and Simulation of a Micro Piezoelectric Energy Harvester Based on a Mass Proof Cantilever.
    Felipe Oliveira and Davies Monteiro.
  2. Morphology study of Gold electrolytic-thin-films for applications in MCM-D.
    Melissa Mederos Vidal, Cristina Battesini Adamo, Alexander Flacker and Ricardo Cotrin Teixeira.
  3. Hydrogenated amorphous silicon deposited by ECR-CVD for hybrid a-Si:H-p+/c-Si-n++ solar cells.
    Hugo Alvarez, Audrey Silva, Frederico Cioldin and José Diniz.
  4. FTIR and IES Characterization of Fresh and Passivated Macroporous Silicon.
    Rosimara Toledo, Carlos Dias, Danilo Huanca and Walter Salcedo.
  5. Flip Chip Technology using Gold Stud Bumps.
    Mariza Aparecida Dias, Richard Marc Richter and Ricardo Cotrin Teixeira.
  6. An alternative pathway to MEMS development in Brazil: conventional, modified and novel devices.
    Vinicius Azevedo de Souza E Vecchia, Marina Antônia de Carvalho Salmen and Davies William de Lima Monteiro.
  7. Self Phase Modulation measurement of the nonlinear index of HfO2.
    Daniel Orquiza de Carvalho, Hugo Enrique Hernandez-Figueroa and Michal Lipson.
  8. Mode analysis modeling of optical waveguide scattering losses.
    Emerson G. Melo, Daniel Orquiza de Carvalho and Marco I. Alayo.
  9. Field Effect Transistors based on Graphene Micro Channels Defined by Photolithography.
    Aline Pascon, Dunieskys Larrude and José A. Diniz.
  10. Design and fabrication of a three-dimensional microcoil for the development of an integrated LTCC-PDMS microvalve for analytical chemistry microsystem.
    Reinaldo Lucas Dos Santos Rosa, Antonio Seabra and Antonio Domingues Dos Santos.
  11. Silicon Surface Modification and its Characterization by IES and RBS.
    Danilo Huanca and Walter Salcedo.
  12. XRR, GISAXS and SEM Characterization of Low-k Porous Carbon Doped Silicon Dioxide Thin Film.
    Danilo Huanca, Rosimara Toledo, Carlos Dias, Sebastiao Gomes and Patrick Verdonk.
  13. Microfabrication, Strain Characterization by Raman Spectroscopy and FEM Simulation of Suspended Strained Silicon Micro-bridges.
    Jose Luis Arrieta, Lucas Spejo, Angelica D. de Barros, Roberto L. de Orio and Jose Alexandre Diniz.
  14. Influence of electrode distance on porous silicon supercapacitor internal resistance.
    Marcel Castilho Batista de Carvalho and Sebastião Gomes Dos Santos Filho.
  15. NUMERICAL SIMULATION OF STRESSMIGRATION IN INTERCONNECTS WITH AIR-GAP STRUCTURES.
    Estevao Magro and Roberto Ório.
  16. Simulations of SPM, XPM and FWM in Single-Mode Fiber Optic Networks.
    Fabio de Sousa, Marcos Benedito Costa, Jorge Everaldo de Oliveira, Fiterlige Martins de Sousa and Elizete Rego Sabino.
  17. Development of gas aggregation source and radial magnetron sputtering for the production of core@shell metallic nanoparticles.
    Valquiria Lima, Antonio Santos, Douglas Santos and Sergio Romero.


  18. Devices


  19. Logic Inverter SOI MOSFET Operating at High Temperature.
    Fernando Ribeiro and Marcello Bellodi.
  20. BE SOI MOSFET: A very simple reconfigurable SOI transistor.
    Leonardo S. Yojo, Ricardo C. Rangel, Kátia R. A. Sasaki and João Antonio Martino.
  21. Minimal Design of a Reconfigurable Carbon Nanotube FET.
    Rebeca S. Moura and Stefan Blawid.
  22. Influence of the dimensions on pFinFET devices towards the self-heating effect.
    Carlos A. B. Mori, Paula G. D. Agopian and João A. Martino.
  23. Back Gate Bias Influence on Threshold Voltage at pMOS and nMOS SOI Ω-gate Nanowire down to 10nm Width.
    Vitor Itocazu, Luciano Almeida, Victor Sonnenberg, Paula Agopian, Sylvain Barraud, Maud Vinet, Olivier Faynot and Joao Martino.
  24. Influence of low energy proton irradiation on nanowire transistor SOI devices.
    Fernando Teixeira, Paula Agopian and João Martino.
  25. Silicon Photonics and RF Hybridization Approach for Optical Solutions.
    Celio Finardi, Stefan Tenenbaum, Andre Ponchet and Roberto Panepucci.
  26. Low-Frequency Noise Analysis of the Asymmetric Self-Cascode Structure Composed by FD SOI nMOSFETs.
    Rafael Assalti and Michelly de Souza.
  27. THE CHANNEL LENGTH INFLUENCE ON THE LOW FREQUENCY NOISE IN GC SOI nMOSFETS WITH THIN OXIDE LAYER.
    Allan Molto and Marcelo Pavanello.
  28. Tridimensional Numerical Simulation and Electrical Characterization of Stacked Nanowires SOI MOSFETs.
    Bruna Paz and Marcelo Pavanello.
  29. Electrolyte-Insulator-Semiconductor device with integrated titanium nitride reference electrode for pH detecting.
    Rodrigo César, Ioshiaki Doi, José Diniz and Jacobus Swart.
  30. Study of the Annular Ellipsoidal Layout Style for MOSFETs in X-rays Ionizing Radiation Environments.
    William Souza Da Cruz, Salvador Pinillos Gimenez and Luis Eduardo Seixas.
  31. Analysis of Self-Heating Effects in Junctionless Nanowire Transistors Through Current Transients.
    Flávio Enrico Bergamaschi and Marcelo Antonio Pavanello.
  32. Channel Length Influence on a Self-aligned Triple Gate SOI Tunnel FET.
    Henrique Torres, Paula Agopian, João Martino, Cor Claeys, Eddy Simoen, Rita Rooyackers and Anne Vandooren.
  33. ZTC Spread Region in Strained and Irradiated nFinFETs.
    Vinicius Nascimento, Paula Agopian, Eddy Simoen, Cor Claeys and Joao Martino.
  34. Silicon Thickness and Ground Plane Influence on Threshold Voltage and Subthreshold Swing of UTBOX and UTBB SOI nMOSFETs.
    Vanessa Silva, Victor Sonnenberg, Joao Martino and Paula Agopian.
  35. Analysis of different source materials on the drain current of nTFETs.
    Caio Cesar Mendes Bordallo, Joao Martino, Paula Agopian, Alireza Alian, Yves Mols, Rita Rooyackers, Anne Vandooren, Anne Verhulst, Eddy Simoen, Cor Claeys and Nadine Collaer.
  36. Modelling of MOS devices for solar energy harvesting.
    Fábio Izumi and Sebastião Santos Filho.
  37. Process simulation of UTBOX SOI Devices for 1T-DRAM Memory Application.
    Luis Felipe Oliveira Bergamim and Maria Gloria Cano de Andrade.
  38. Analysis of Thermal Resistance with BOX Thinning in UTB SOI MOSFETs.
    Fernando J. Costa.
  39. Simulation Analysis of Fin Width Influence in Junctionless MOSFET Effective Mobility: from Quasi-Planar to Nanowires.
    Thales Augusto Ribeiro, Marcelo Antonio Pavanello and Antonio Cerdeira.
     


  40. Design


  41. Performance of an Oscillator with Bipolar Junction Transistors Operating at Ultralow Voltage.
    Antonio Telles, Marcos Andrade, Jose Antenor Pomilio and Saulo Finco.
  42. Verification Challenges in Analog-Digital Interfaces.
    Vinicius Martins, Wang Chau, Jerson Guex and Márcio H. G. Oliveira.
  43. Development of Micro-Trafos Using MCM and Electronic Packaging Technologies.
    Marinalva Muniz Rocha, Antonio Carlos Costa Telles and Ricardo Cotrin Teixeira.
  44. Design of an Eight-Terminal piezotransducer using Multiphysic simulators.
    Jose Ramirez and Fabiano Fruett.
  45. Voltage-to-Frequency Converter Design for System-on-Chip Testing in 0.35um CMOS Technology.
    Luis Chaparro, Juan Carrillo, Hugo Hernandez and Wilhelmus Van Noije.
  46. OPTIMIZATION OF AN OTA BY USING A DEDICATED CAD TOOL WITH DIFFERENT HEURISTIC ALGORITHMS OF ARTIFICIAL INTELIGENCE.
    Marcelo Machado Aoyama, Rodrigo Alves de Lima Moreto and Salvador Pinillos Gimenez.
  47. A 0.5V 2.4GHz Low Power Cross-Coupled Voltage Controlled Oscillator for a BLE Receiver.
    Fellipe Sola, Lucas C. Severo, Hugo Daniel Hernandez, Roberto Rangel, Daniele S. Santos, Walter C. Aranda and Wilhelmus A. M. V. Noije.
  48. Verifying the Interface between a Digital Windowing Block and a Sigma-Delta Analog to Digital Converter.
    Vinicius Martins, Roberto Rangel and Wang Chau.
  49. A Functional Verification Method for an All-Digital Automatic Gain Control Block.
    Marcio Oliveira, Vinicius Martins and Wang Chau.
  50. A Bluetooth Low Energy system analysis for low power applications.
    Roberto Silva, Lucas Compassi Severo, Fellipe Sola, Hugo Hernandez, Daniele Dos Santos, Walter C. Aranda and Wilhelmus Van Noije.
  51. Study of ADS1299 for EEG Signals Acquisition.
    Juliana Fernandes and Maria Claudia F. Castro.
  52. Ring Oscillators: Comparative Approach for SET Tolerant Structures.
    Raphael Ronald Noal Souza and Agord De Matos Pinto Jr.
  53. Signal windowing models implementation comparison for signal analysis in a SBCD (Brazilian Data Collection System) satellite transponder project.
    Everton Souza, Vinicius Martins and Renan Toniolo.


Past years

2014
2015
2016